Developments in the semiconductor industry have over the years been aimed at creating higher performance devices at competitive or lower prices. These developments have resulted in extreme miniaturization of semiconductor devices, which has been made possible by numerous and mutually supporting advances in semiconductor processes and by advances in the materials that are used for the creation of semiconductor devices. While most semiconductor devices are aimed at processing digital data, dynamic random access memory (DRAM) storage devices incorporate data retention or storage capabilities. The creation of capacitive components, which are the basis for the data storage capabilities of DRAM devices, must emphasize that these capacitive components are created on a relatively small surface area of a semiconductor substrate while using methods and procedures that are well known in the art of creating semiconductor devices.
It is well known that capacitors can be created between layers of metal or polysilicon. Capacitors can be either of a planar design, for reasons of process simplicity, or can be three-dimensional, resulting in a smaller footprint as commonly used in DRAM devices.
DRAM devices typically consist of arrays of memory cells that perform two basic functions, namely data access controlling performed by a transistor and data retaining performed by a capacitor. Binary data is stored as electrical charges in the capacitors in DRAM memory cells. Contacts to the surrounding circuits are provided for the DRAM memory cells. DRAM memory is so named because DRAM cells can retain information only for a limited period of time before they must be read and refreshed at periodic intervals. In a typical DRAM construction, one side of the transistor is connected to one side of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connect points that form bit and word lines. The other side of the capacitor is connected to a reference voltage.
DRAM cells can be formed using a capacitor-over-bitline (COB) scheme or a capacitor-under-bitline (CUB) scheme. In a COB scheme, capacitors are formed over the bitline to which the capacitors are coupled, while in a CUB scheme, capacitors are formed under the bitline to which the capacitors are coupled. Typically, memory cells formed using CUB scheme are preferred by embedded DRAM applications although they have higher bitline coupling noise than memory cells formed using a COB scheme.
High performance is demanded for embedded DRAM cells, particularly embedded DRAM cells for system on chip (SOC) applications. Among the performance requirements, bitline sensing speed and sensing margin are important performance criteria that affect the speed and reliability of DRAM cells.
Bitline sensing speed and signal sensing margin are both affected by bitline parasitic capacitance. The sense signal ΔV, which is a signal detected by a sense amplifier to distinguish a state of the memory cell, can be generally expressed as:ΔV=½Vcc/(1+Cbl/Cs)  [Eq. 1]wherein Vcc is the operation voltage of the memory device, Cbl is bitline parasitic capacitance, and Cs the capacitance of the capacitor storing charges.
If bitline parasitic capacitance Cbl is reduced, the sense signal ΔV detected by the sense amplifier increases, thus reducing the probability of a read error. Additionally, if the bitline parasitic capacitance Cbl reduces, fewer charges will be required to charge and discharge parasitic capacitors, resulting in an increased memory access speed.
Therefore, in order to form dynamic random access memory having high speed and high reliability, bitline parasitic capacitance needs to be reduced.